Important components in implementing SMS4 cryptographic procedure (or algorithm) include a key expansion unit and an encryption and decryption unit, the internal structures and processing processes of which are basically the same or very similar. The encryption and decryption unit can consist of three parts, e.g., a data registering unit, a constant array storing unit and a data converting unit.
The data registering unit generally consists of a general trigger for registering data. The data registered in the unit can be unchanged within a clock period. The general trigger can be a data temporary storage component where the data of a data input end is sent to an output end of the trigger at a rising clock edge or a falling clock edge, while the data of the trigger output end may be unchanged at other time.
The constant array storing unit can be a storing unit for storing a constant array. The convention constant array may be generally a data array with 32-bit width and 32-bit depth prepared before encryption and decryption processing. The data in the constant array storing unit can be arranged in a descending sequence of addresses, and named as rk0, rk1 . . . rk31.
The data converting unit can be a unit for data processing according to the cryptographic procedure or algorithm. For example, in the data processing according to the National SMS4 cryptographic procedure/algorithm, the operation performed by the data converting unit only includes one conversion specified in the cryptographic procedure/algorithm.
Conventionally, the encryption and decryption data processing method according to SMS4 cryptographic procedure/algorithm may be as follows:                1) inputting external data into the data registering unit; in particular, data are outputted from the output end of the data registering unit after the external data are inputted into the data registering unit; for example, the external data of 128 bits may be divided into four data blocks with each including 32 bits, and named as A0, A1, A2 and A3, respectively; the data outputted from the output end of the data registering unit are still in 128 bits, which may be divided into four data blocks with each including 32 bits, and named as a0, a1, a2 and a3, respectively;        2) providing a data conversion processing, with the data from the output end of the data registering unit being inputted into the data converting unit for data conversion processing; for example, the data a0, a1, a2 and a3 from the output end of the data registering unit may be converted into 128-bit data C0, C1, C2 and C3 via the data converting unit;        3) providing a second data conversion processing, with the data after the previous data conversion processing being stored into the data registering unit again, then the data from the output end of the data registering unit can be inputted the data converting unit again for a second data conversion processing; and        4) repeating the second data conversion processing for obtaining the final data processing result.        
For external data with 128 bits, the second data conversion processing may be repeated 30 times, e.g., the data conversion processing shall be made 32 times in all for obtaining the final data processing result.
In the conventional systems and methods described above, a constant array with 32-bit width and 32-bit depth is generally prepared before the encryption and decryption processing, and the data converting unit performs only one conversion operation specified in the cryptographic algorithm, as a result, the data conversion processing shall be repeated many times. For example, in order to encrypt 128-bit data using such conventional systems and methods, the data conversion processing generally has to be repeated 32 times for obtaining the final data processing result.
Furthermore, the encryption and decryption efficiency of the conventional systems and methods described above is generally low. The encryption efficiency is the data amount encrypted in unit time. For example, the data conversion processing is likely repeated 32 times for encrypting 128-bit data. Due to the generally-low clock frequency in current practical applications, the amount of data encrypted in unit time may be less, and the efficiency can be low. If the encryption efficiency is specified, the clock frequency should be increased. However, in the practical applications, the clock frequency may be difficult to increase. Therefore, the actual encryption efficiency is still low. The increase of the clock frequency likely further causes difficulties in design and implementation of the integrated circuit, and a poor signal integrity and a higher design cost. Furthermore, the integrated circuit designed according to the conventional systems which utilize the conventional methods, may also result in the increasing of cost of a Printed Circuit Board (PCB), and the difficulties in designing the PCB and product implementation; additionally, great interferences may be present in the system, which impacts on the normal and high-efficiency work of other equipments and devices.